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ICS9LRS4103 idt ? pc main clock 1520a?03/16/10 32-pin ck505 f or intel systems 1 da t asheet pin configuration recommended application: ck505 clock, 32-pin for 5 series intel chipsets output features:? 1 - cpu differential low power push-pull pairs ? 1 - src differential low power push-pull pairs ? 1 - selectable 120mhz ck_ssc_disp or 100 mhz src lowpower push-pull pair ? 1 - sa t a/src selectab le diff erential lo w po w er push-pull pair ? 1 - do t diff erential lo w po w er push-pull pair ? 1 - ref , 14.318mhz ke y specifications: ? cpu outputs cycle-cycle jitter < 85ps ? src output cycle-cycle jitter < 125ps ? +/- 100ppm frequency accur acy on all outputs ? src are pcie gen2 compliant features/benefits:? supports spread spectrum modulation, default is 0.5%down spread ? uses external 14.318mhz crystal, external crystal loadcaps are required for frequency tuning ? does not require external pass transistor for voltageregulator ? integ r ated 33 ser ies resistors on diff erential outputs , z o=50 t ab le 1: cpu frequenc y select t ab le gndxtal sel_sata_ns# vddxtal gndref ref14.318m/fslc** vddref14m ckpwrgd/pd#_3.3 vddcpu 32 31 30 29 28 27 26 25 x1 1 24 cpuc0 x2 2 23 cput0 smbclk_3.3 3 22 gndcpu smbdat_3.3 4 21 sel_120m# vdd96 5 20 vddsrc dot96t 6 19 src2c dot96c 7 18 src2t gnd96 8 17 gndsrc 9 10 11 12 13 14 15 16 gndssc ck_ssc_disp_t ck_ssc_disp_c vddssc vddsata src1t/sata_ns_t src1c/sata_ns_c gndsata ** internal pull-down resistor 9lrs4103 fs l c b0b7 cpu mhz src mhz ref mhz dot mhz 0 (default) 133.33 1 100.00 1. fs l c is a low-threshold input.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 100.00 14.318 96.00 sel_120m# pin# 21 pin# 10/11 pulled low 120mhz pulled high 100mhz sel_sata_ns# pin# 31 pin# 14/15 0 100mhz_nonss 1 100mhz_ss
idt ? pc main clock 1520a?03/16/10 ICS9LRS4103 pc main clock 2 pin description pin# pin name type pin description 1 x1 in crystal input, nominally 14.318mhz. 2 x2 out crystal output, nominally 14.318mhzmhz. 3 smbclk_3.3 in clock pin of smbus circuitry, 3.3v tol erant. 4 smbdat_3.3 i/o data pin for smbus circuitry, 3.3v to lerant. 5 vdd96 pwr power pin for the dot96mhz output 3.3v. 6 dot96t out true clock dot96 output with integrated 33ohm serie s resistor. no 50ohm resistor to gnd needed. 7 dot96c out complementary clock dot96 output with integrated 33 ohm series resistor. no 50ohm resistor to gnd needed. 8 gnd96 pwr ground pin for the dot96mhz output. 9 gndssc pwr ground pin for the ck_ssc_disp output. 10 ck_ssc_disp_t out true clock of ck_ssc_disp (100mhz or 120mhz) output with integrated 33ohm series resistor. no 50ohm resistor to gnd ne eded. 11 ck_ssc_disp_c out complementary clock of ck_ssc_disp (100mhz or 120mh z) output with integrated 33ohm series resistor. no 50ohm resisto r to gnd needed. 12 vddssc pwr power pin for the ck_ssc_disp output 3.3 v 13 vddsata pwr power pin for the sata output 3.3v 14 src1t/sata_ns_t out true clock of differential 0.8v push-pull src/sata output with integrated 33ohm series resistor. no 50ohm resistor to gnd ne eded. 15 src1c/sata_ns_c out complementary clock of differential 0.8v push-pull src/sata output with integrated 33ohm series resistor. no 50ohm resisto r to gnd needed. 16 gndsata pwr ground pin for the sata output. 17 gndsrc pwr ground pin for the src output. 18 src2t out true clock of differential 0.8v push-pull src outp ut with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 19 src2c out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resisto r to gnd needed. 20 vddsrc pwr power pin for the src output 3.3v. 21 sel_120m# in selects pins #10/11 to be 120mhz or 10 0mhz. "0" = 120mhz, "1" = 100mhz. 22 gndcpu pwr ground pin for the cpu output. 23 cput0 out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd ne eded. 24 cpuc0 out complementary clock of differential pair 0.8v push- pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resisto r to gnd needed. 25 vddcpu pwr power pin for the cpu output 3.3v 26 ckpwrgd/pd#_3.3 in notifies ck505 to sample latched inputs, or iamt en try/exit, or pwrdwn# mode 27 vddref14m pwr power pin for the ref output 3.3v 28 ref14.318m_3x/fslc** i/o reference 14.318 mhz clock, which drives 3 loads on default / 3.3v tolerant input for cpu frequency selection. refer to input e lectrical characteristics for vil_fs and vih_fs values. 29 gndref pwr ground pin for the ref output. 30 vddxtal pwr power pin for xtal 3.3v 31 sel_sata_ns# in selects pin #14/15 to be src1 or sa ta_ns. "0" = sata_ns, "1" = src1 32 gndxtal pwr ground pin for xtal.
idt ? pc main clock 1520a?03/16/10 ICS9LRS4103 pc main clock 3 ICS9LRS4103 is compatib le with the intel ck505 y ello w co v er specification. this cloc k synthesiz er pro vides a single chip solution f or intel desktop 5 series chipsets. ICS9LRS4103 is driven with a 14.318mhz crystal. it also provides a tight ppm accuracy output for serial at a and pci-express suppor t. general descriptionbloc k dia gram pll2 dot96 (non-ss) pll1 cpu/src (ss) div div div div cpu 100/133mhz src 100mhz sata (non-ss/ss) 100mhz dot96mhz (non-ss) ref 14.318mhz pll3 ssc_disp (ss) ssc_disp 120/100mhz 14.318m
idt ? pc main clock 1520a?03/16/10 ICS9LRS4103 pc main clock 4 absolute maximum ratings parameter symbol conditions min max units notes maximum supply voltage vddxxx core/logic supply 4.6 v 1,7 maximum supply voltage vddxxx_io low voltage differen tial i/o supply 3.8 v 1,7 maximum input voltage v ih 3.3v lvttl inputs 4.6 v 1,7,8 minimum input voltage v il any input gnd - 0.5 v 1,7 storage temperature ts - -65 150 c 1,7 case temperature tcase - 115 c 1,7 input esd protection esd prot human body model 2000 v 1, 7 electrical characteristics - input/supply/common ou tput parameters parameter symbol conditions min max units notes ambient operating temp tambient - 0 70 c 1 supply voltage vddxxx supply voltage 3.135 3.465 v 1 input high voltage v ihse single-ended inputs 2 v dd + 0.3 v 1 input low voltage v ilse single-ended inputs v ss - 0.3 0.8 v 1 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input leakage current i inres inputs with pull or pull down resistors v in = v dd , v in = gnd -200 200 ua 1 output high voltage v ohse single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v olse single-ended outputs, i ol = 1 ma 0.4 v 1 output high voltage v ohdif differential outputs 0.7 0.9 v 1 output low voltage v oldif differential outputs 0.4 v 1 low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 vdd + 0.3 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 operating supply current i dd 3.3v supply 100 ma 1 power down current i dd_pd3.3 3.3v supply, power down mode 6 ma 1 iamt mode current i dd_iamt3.3 3.3v supply, iamt mode 50 ma 1 input frequency f i v dd = 3.3 v 14.3182 mhz 2 pin inductance l pin 7 nh 1 c in logic inputs 1.5 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 6 pf 1 spread spectrum modulation frequency f ssmod triangular modulation 30 33 khz 1 input capacitance
idt ? pc main clock 1520a?03/16/10 ICS9LRS4103 pc main clock 5 ac electrical characteristics - input/common parame ters parameter symbol conditions min max units notes clk stabilization tstab from vdd power-up or de-assertion of pd# to 1st clock 1.8 ms 1 tfall_pd# tfall 5 ns 1 trise_pd# trise 5 ns 1 fall/rise time of pd#, pci_stop# and cpu_stop# inputs ac electrical characteristics - low power different ial outputs parameter symbol conditions min max units notes rising edge slew rate tslr differential measurement 2. 5 4 v/ns 1,2 falling edge slew rate tflr differential measurement 2 .5 4 v/ns 1,2 slew rate variation tslvar single-ended measurement 20 % 1 maximum output voltage vhigh includes overshoot 1150 mv 1 minimum output voltage vlow includes undershoot -300 mv 1 differential voltage swing vswing differential measur ement 300 mv 1 crossing point voltage vxabs single-ended measurement 300 550 mv 1,3,4 crossing point variation vxabsvar single-ended measu rement 140 mv 1,3,5 duty cycle dcyc differential measurement 45 55 % 1 cpu jitter - cycle to cycle cpujc2c differential measurement 85 ps 1 src jitter - cycle to cycle srcjc2c differential measurement 125 ps 1 dot jitter - cycle to cycle dotjc2c differential measurement 250 ps 1 src skew srcskew differential measurement, all src from same pll 200 ps 1 electrical characteristics - ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values 0 0 ppm 1,6 clock period tperiod 14.318180 mhz output nominal 69.8 413 69.8413 ns 6 absolute min/max period tabs 14.318180 mhz including cycle to cycle jitter 68.8413 70.84128 ns 6 output high voltage voh ioh = -1 ma 2.4 v 1 output low voltage vol iol = 1 ma 0.4 v 1 output high current ioh voh @min = 1.0 v, voh@max = 3.135 v -33 -33 ma 1 output low current iol vol @min = 1.95 v, vol @max = 0.4 v 30 38 ma 1 rising edge slew rate tslr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate tflr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle dt1 vt = 1.5 v 45 55 % 1 jitter tjcyc-cyc vt = 1.5 v 1000 ps 1
idt ? pc main clock 1520a?03/16/10 ICS9LRS4103 pc main clock 6 electrical characteristics - smbus interface parameter symbol conditions min max units notes smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v olsmb @ i pullup 0.4 v 1 current sinking at v olsmb = 0.4 v i pullup smb data pin 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 maximum smbus operating frequency f smbus block mode 100 khz 1 notes on electrical characteristics: 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around d ifferential zero 3 vxabs is defined as the voltage where clk = clk# 4 only applies to the differential rising edge (clk r ising and clk# falling) 6 all long term accuracy and clock period specificati ons are guaranteed assuming that ref has been tuned to exactly 14.318180 mhz 8 maximum input voltage is not to exceed maximum vdd 5 defined as the total variation of all crossing volt ages of clk rising and clk# falling. matching appli es to rising edge rate of clk and falling edge of clk#. it is measured using a +/-75mv window centere d on the average cross point where clk meets clk#. the average cross point is used to calculate the voltage thresholds the oscilloscope i s to use for the edge rate calculations. 7 operation under these conditions is neither implied , nor guaranteed.
idt ? pc main clock 1520a?03/16/10 ICS9LRS4103 pc main clock 7 cpu src dot96 ck_ssc_disp 100 100 100 100 ppm 50 125 250 125 ps -0.50% -0.50% 0 -0.50% % clock periods - differential outputs with spread sp ectrum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2 src 100.00 9.87400 9.99900 10.00000 10.00100 10.12600 ns 1, 2 ck_ssc_disp 120.00 8.20750 8.33250 8.33333 8.33417 8.4591 7 ns 1,2 dot96 96.00 10.16563 10.41563 10.41667 10.41771 10.66771 n s 1,2 clock periods - differential outputs with spread sp ectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.5 8830 ns 1,2 src 99.75 9.87406 9.99906 10.02406 10.02506 10.02607 10.05 107 10.17607 ns 1,2 ck_ssc_disp 119.70 8.20755 8.33255 8.35338 8.35422 8.3550 5 8.37589 8.50089 ns 1,2 1 guaranteed by design and characterization, not 100% tested in production. notes differential clock tolerances 2 all long term accuracy specifications are guarantee d with the assumption that the crystal input is tun ed to exactly 14.31818mhz. measurement window units ssc on center freq. mhz notes ppm tolerance cycle to cycle jitter cpu measurement window units spread ssc off center freq. mhz cpu
idt ? pc main clock 1520a?03/16/10 ICS9LRS4103 pc main clock 8 table 1: cpu frequency select table fs l c b0b7 cpu mhz src mhz ref mhz dot mhz 0 (default) 133.33 1 100.00 1. fs l c is a low-threshold input.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 100.00 14.318 96.00 table 2: io_vout select table b9b2 b9b1 b9b0 io_ vout 0 0 0 0.3v 0 0 1 0.4v 0 1 0 0.5v 0 1 1 0.6v 1 0 0 0.7v 1 0 1 0.8v 1 1 0 0.9v 1 1 1 1.0v table 3: device id table comment 0 0 0 0 56 pin tssop 0 0 0 1 64 pin tssop 0 0 1 0 reserved 0 0 1 1 reserved 0 1 0 0 reserved 0 1 0 1 72 pin qfn 0 1 1 0 reserved 0 1 1 1 reserved 1 0 0 0 32 pin qfn 1 0 0 1 reserved 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved b8b7 b8b6 b8b5 b8b4 table 4: series resistors for ref output number of loads to drive ref strength rs 1 1x 33 [39 ] 1 2x 39 [43 ] 2 2x 27 [33 ] notes: 2. desktop/mobile platforms with zo = 50/55 ohms us e the first resistor value. 3. systems with zo = 60 ohms use the resistor value s in brackets [ ]. 1. preferred drive strengths using ck505 clock sour ces. transmission d.c.drive strength
idt ? pc main clock 1520a?03/16/10 ICS9LRS4103 pc main clock 9 pd# power management device state w/o latched input w/latched input latches open power down m1 virtual power cycle to latches open single-ended clocks differential clocks low hi-z ck= pull down, ck# = low ck= pull down, ck# = low ck= pull down, ck# = low cpu0 ck= pull down, ck# = low ck= pull down ck# = low ck= pull down ck# = low ck= pull down ck# = low running
idt ? pc main clock 1520a?03/16/10 ICS9LRS4103 pc main clock 10 general smbus serial interface inf ormation f or the ICS9LRS4103 ho w to write: ? controller (host) sends a star t bit. ? controller (host) sends the wr ite address d2 (h) ? ics cloc k will ac kno wledg e ? controller (host) sends the beginning b yte location = n ? ics cloc k will ac kno wledg e ? controller (host) sends the data b yte count = x ? ics cloc k will ac kno wledg e ? controller (host) star ts sending byte n thr ough byte n + x -1 ? ics cloc k will ac kno wledg e each b yte one at a time ? controller (host) sends a stop bit ho w to read: ? controller (host) will send star t bit. ? controller (host) sends the wr ite address d2 (h) ? ics cloc k will ac kno wledg e ? controller (host) sends the begining b yte location = n ? ics cloc k will ac kno wledg e ? controller (host) will send a separ ate star t bit. ? controller (host) sends the read address d3 (h) ? ics cloc k will ac kno wledg e ? ics cloc k will send the data b yte count = x ? ics cloc k sends byte n + x -1 ? ics cloc k sends byte 0 thr ough b yte x (if x (h) was written to b yte 8) . ? controller (host) will need to ac kno wledge each b yte ? controller (host) will send a not ac kno wledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge p stop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt ? pc main clock 1520a?03/16/10 ICS9LRS4103 pc main clock 11 byte 0 fs readback and pll selection register bit pin name description type 0 1 default 7 fslc cpu freq. sel. bit r latch 6 reserved reserved rw - - 0 5 reserved reserved rw - - 1 4 iamt_en set via smbus rw (sticky 1) legacy mode iamt enabled 0 3 reserved reserved rw 0 2 sel_120m# selects pins #10/11 to be 120mhz or 100mhz r 120mhz 100mhz latch 1 sel_sata_ns# select source for sata clock r sata (100mhz_nonss) src1 (100mhz ss) latch 0 pd_restore 1 = on power down de-assert return to last known state 0 = clear all smbus configurations as if cold power - on and go to latches open state this bit is ignored and treated at '1' if device is in iamt mode. rw configuration not saved configuration saved 1 byte 1 cpu/src spread selection register bit pin name description type 0 1 default 7 reserved reserved rw - - 0 6 ck505 pll1_ssc_sel select 0.5% down or center ssc rw down spread center spread 0 5 reserved reserved rw - - 0 4 reserved reserved rw - - 0 3 reserved reserved rw - - 0 2 reserved reserved rw - - 0 1 reserved reserved rw - - 1 0 reserved reserved rw - - 1 byte 2 output enable register bit pin name description type 0 1 default 7 ref_3l_oe output enable for ref0 rw output disabled output enabled 1 6 reserved reserved rw - - 1 5 reserved reserved rw - - 1 4 reserved reserved rw - - 1 3 reserved reserved rw - - 1 2 reserved reserved rw - - 1 1 reserved reserved rw - - 1 0 reserved reserved rw - - 1 byte 3 reserved register bit pin name description type 0 1 default 7 reserved reserved rw - - 1 6 reserved reserved rw - - 1 5 reserved reserved rw - - 1 4 reserved reserved rw - - 1 3 reserved reserved rw - - 1 2 reserved reserved rw - - 1 1 reserved reserved rw 1 0 reserved reserved rw - - 1
idt ? pc main clock 1520a?03/16/10 ICS9LRS4103 pc main clock 12 byte 4 output and spread spectrum enable register bit pin name description type 0 1 default 7 ck_ssc_disp output enable for ck_ssc_disp rw output d isabled output enabled 1 6 sata/src1_oe output enable for sata/src1 rw output disabled output enabled 1 5 src2_oe output enable for src2 rw output disabled output enabled 1 4 dot96_oe output enable for dot96 rw output disabled output enabled 1 3 reserved reserved rw - - 1 2 cpu0_oe output enable for cpu0 rw output disabled output enabled 1 1 pll1_ssc_on enable pll1's spread modulation rw spread disabled spread enabled 1 0 pll3_ssc_on enable pll3's spread modulation rw spread disabled spread enabled 1 byte 5 reserved register bit pin name description type 0 1 default 7 reserved reserved rw - - 0 6 reserved reserved rw - - 0 5 reserved reserved rw - - 0 4 reserved reserved rw - - 0 3 reserved reserved rw - - 0 2 reserved reserved rw - - 0 1 reserved reserved rw - - 0 0 reserved reserved rw - - 0 byte 6 reserved register bit pin name description type 0 1 default 7 reserved reserved rw - - 0 6 reserved reserved rw - - 0 5 reserved reserved rw - - 0 4 reserved reserved rw - - 0 3 reserved reserved rw - - 0 2 reserved reserved rw - - 0 1 reserved reserved rw - - 0 0 reserved reserved rw - - 0 byte 7 vendor id/ revision id bit pin name description type 0 1 default 7 rev code bit 3 r x 6 rev code bit 2 r x 5 rev code bit 1 r x 4 rev code bit 0 r x 3 vendor id bit 3 r 0 2 vendor id bit 2 r 0 1 vendor id bit 1 r 0 0 vendor id bit 0 r 1 byte 8 device id and output enable register bit pin name description type 0 1 default 7 device_id3 r 1 6 device_id2 r 0 5 device_id1 r 0 4 device_id0 r 0 3 reserved reserved rw - - 0 2 reserved reserved rw - - 0 1 reserved reserved rw - - 0 0 reserved reserved rw - - 0 revision id vendor specific table of device identifier codes, used for differentiating between ck505 package options, etc. 32-pin device vendor id ics is 0001, binary
idt ? pc main clock 1520a?03/16/10 ICS9LRS4103 pc main clock 13 byte 9 amplitude control register bit pin name description type 0 1 default 7 reserved reserved rw - - 0 6 reserved reserved r - - 0 5 ref strength sets the ref output drive strength rw 1x (2loads) 2x (3 loads) 1 4 reserved reserved rw - - 0 3 reserved reserved rw - - 0 2 io_vout2 io output voltage select (most significant bit) rw 1 1 io_vout1 io output voltage select rw 0 0 io_vout0 io output voltage select (least significan t bit) rw 1 byte 10 reserved register bit pin name description type 0 1 default 7 reserved reserved rw - - 0 6 reserved reserved rw - - 0 5 reserved reserved rw - - 0 4 reserved reserved rw - - 0 3 reserved reserved rw - - 0 2 reserved reserved rw - - 0 1 reserved reserved rw - - 1 0 reserved reserved rw - - 1 byte 11 iamt enable register bit pin name description type 0 1 default 7 reserved reserved rw 0 6 reserved reserved rw 0 5 reserved reserved rw 0 4 reserved reserved rw 1 3 reserved reserved rw - - 0 2 cpu0_amt_en m1 mode clk enable rw disable enable 1 1 pci-e_gen2 determines if pci-e gen2 compliant r non-g en2 pci-e gen2 compliant 1 0 reserved reserved rw - - 1 byte 12 byte count register bit pin name description type 0 1 default 7 reserved rw 0 6 reserved rw 0 5 bc5 rw 0 4 bc4 rw 0 3 bc3 rw 1 2 bc2 rw 1 1 bc1 rw 0 0 bc0 rw 1 read back byte count register, max bytes = 32 see table 2: v_io selection (default is 0.8v)
idt ? pc main clock 1520a?03/16/10 ICS9LRS4103 pc main clock 14 n 32 a 0.8 1.0 n d 8 a1 0 0.05 n e 8 a3 b 0.18 0.3 e d x e basic d2 min. / max. 3.0 3.3 e2 min. / max. 3.0 3.3 l min. / max. 0.3 0.5 thermally enhanced, very thin, fine pitch quad flat / no lead plastic package symbol 32l max. min. symbol dimensions dimensions (mm) 5.00 x 5.00 0.50 basic 0.20 reference e top view or anvil singulation a3 l n (ref.) e e e e (ref. ) (ref. ) (ref. ) (typ.) if a1 even e2 d2 d2 2 a c 0.08 c e2 2 2 2 1 sawn singulation index area seating plane are even thermal base odd b (n - 1)x n 1 chamfer 4x 0.6 x 0.6 max optional d d & & n d n d n e n e & n d n e (n - 1)x e marking diagram ordering information part / order number shipping packaging package tempera ture 9lrs4103bklf tubes 32-pin mlf 0 to +70c 9lrs4103bklft tape and reel 32-pin mlf 0 to +70c "lf" suffix to the part number are the pb-free conf iguration and are rohs compliant. "b" is the device revision designator (will not cor relate with the datasheet revision). ics rs4103bl yyww origin ######
ICS9LRS4103 pc main clock 15 innovate with idt and accelerate your future networks. cont act: www .idt .com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for t ech support 408-284-6578 pcclockhelp@id t.com corporate headquarters integrated device t echnology , inc. 6024 silver creek v alley road san jose, ca 95138 united s t ates 800 345 7015 +408 284 8200 (out side u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device t echnology , inc. all right s reserved. product specifications subject to change without notice. idt , ics, and the idt logo are trademarks of integrated device t echnology , inc. accelerated thinking is a service mark of integrated device t echnology , inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa this product is protected by united s t ates patent no. 7,342,420 and other p atent s. revision history rev. issue date who description page # 0.1 10/08/08 rdw initial release - 0.2 11/03/08 rdw updated electrical characterisitcs 1) updated idd characteristics for 32-pin parts. o ld idd values were for 56/64 pin devices 2) updated ref to be 0 ppm ? tuned by user with ext ernal load caps. it is not +/-300ppm. 3) minor updates to pagination 4) added connector dot to src output to indicate co nnection. various 0.3 11/05/08 rdw 1) removed reference to wake-on-lan current spec in data sheet, this part does not support wol. 0.4 12/17/08 rdw src skew from: 500ps to: 200ps 0.5 04/13/09 rdw added top-side marking a 03/15/10 rdw 1. updated electrical characteristics per char data 2. added table 4: series resistor values for ref 3. corrected smbus reference to ref strength. ref is 1 load/2load strength. 4. release to final various

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